This week at DesignCon 2012, Apache (an ANSYS subsidiary) held its third annual Chip–Package–System workshop series. What a wonderful opportunity this was to bring together experts from the semiconductor industry to address today’s design challenges. Two separate forums covered the topics of CPS Methodology for Cost-Down and/or Reliability and CPS for 3-D IC and Power–Thermal–Mechanical–Electrical Applications. Semiconductor industry designers and university students filled the hall to learn about these hot topics in design and methodology.
Presenters from Intel and Cisco provided details about CPS methodology. Dr. Mondira (Mandy) Pant from Intel spoke on Power Delivery Network Design of Modern Microprocessors: Getting it Right the First Time, describing the need for a holistic CPS approach to design that incorporates each aspect of the system, the challenges associated with analysis of today’s designs, and suggestions on how to design a robust power delivery network. The information she provided runs parallel with the Apache solution vision of integrated analysis and verification. Such challenges are no longer just the chip designers’ problem, but require that all design parties comprehend and address these from the very beginning of the design process. Dr. Amit Agrawal from Cisco presented Signal and Power Integrity Challenges for High-Speed System Board Design, focusing on high-speed channel modeling, measurement correlation between models and actual design, and expected future challenges as we move to higher data rates. Thao Pham from Intel presented Power Grid Parasitic Impact on System Level Power Integrity, offering information on the utility of a chip power model in the dissection of the impact of various PDN parasitics on the overall impedance of the system.
At the 3-D IC workshop, Dr. Tim Hollis from Micron presented Modeling and Simulation Challenges in 3-D Memories. He focused on Micron’s Hybrid Memory Cube, discussing modeling and simulation techniques for 3-D memories. Ivor Barber of LSI presented Practical Considerations in Selection of 2.5-D/3-D Package Solutions, reviewing the overall landscape of the movement toward MCM, 2.5-D, and 3-D packaging along with the key motivators for adopting these topologies. Dr. Simon Burke from Xilinx presented Challenges and Solutions to Practical 3-D IC Design, outlining the challenges of modeling and simulation in 3-D IC designs for STA, SI, LVS, IR, EM and thermal analysis.
Learn more about the Apache CPS solution.
